1. Field of the Invention
The present invention relates to a semiconductor device such as heterojunction bipolar transistor (HBT) and a method of manufacturing the same. Particularly, the present invention relates to a semiconductor device which ensures electrical isolation between device elements such as HBT and easily achieves high current gain, high reliability, and planarization while reducing collector resistance to enhance the efficiency of an amplifier, and a method of manufacturing the same.
2. Description of Related Art
A typical example of HBT is fabricated on a semi-insulating gallium arsenide (GaAs) substrate. A sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer are epitaxially grown on the semi-insulating GaAs substrate. Further, an emitter electrode, a base electrode, and a collector electrode are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. In a high-power amplifier using the HBT, it is necessary to reduce collector resistance to as low as possible in order to enhance the efficiency, which is one of the important factors for a high-performance amplifier.
In the HBT, a current path is created from the collector layer to the collector electrode through the conductive sub-collector layer. The resistance against the current flowing through the sub-collector layer, which is referred to hereinafter as “access resistance”, constitutes part of the collector resistance. On the other hand, in order to electrically isolate device elements such as transistors from each other, it is necessary to insulate the sub-collector layer between the elements.
FIGS. 1A and 1B show examples of conventional semiconductor devices. On a semi-insulating GaAs substrate 100, a sub-collector layer 101 formed of n-type GaAs, a collector layer 102 formed of n-type or non-doped GaAs, a base layer 103 formed of p-type GaAs, an emitter layer 104 formed of n-type InGaP or AlGaAs lattice-matched to GaAs, an emitter cap layer 105 formed of n-type GaAs, and an emitter cap layer 106 formed of InGaAs are laminated sequentially. Further, an emitter electrode 107 formed of WSi is placed on the emitter cap layer 106. A base electrode 108 formed of Pt/Ti/Pt/Au is placed on the base layer 103. A collector electrode 109 formed of Ni/AuGe/Au is placed on the collector layer 101. These components constitute a HBT device.
In order to insulate the sub-collector layer 101 between device elements, the semiconductor device of FIG. 1A has an element insulating region 110 created by ion implantation, and the semiconductor device of FIG. 1B has an element insulating region 111, which is a recess, formed by removing the sub-collector layer 101 by etching.
A method of manufacturing the semiconductor device is explained hereinafter with reference to FIGS. 2A to 2D, which show the configurations in the course of the process to form the device of FIG. 1.
First, as shown in FIG. 2A, an epitaxial wafer in which the sub-collector layer 101, collector layer 102, base layer 103, emitter layer 104, emitter cap layer 105, and emitter cap layer 106 are sequentially laminated on the substrate 100 is formed. Next, WSi, which serves as the emitter electrode 107, is deposited by sputtering on one surface of the epitaxial wafer. The emitter electrode 107 is then formed by dry etching, using a patterned photoresist mask. Using the emitter electrode 107 as a mask, etching is performed with sulfuric etchant to expose the surface of the emitter layer 104. The emitter cap layers 105, 106, and emitter electrode 107 are thereby shaped as shown in FIG. 2B.
Then, Pt/Ti/Pt/Au is deposited on the emitter layer 104 by evaporation and lift-off process. The Pt/Ti/Pt/Au is sintered by alloy process to contact with the base layer 103, thereby forming the base electrode 108. Then, etching is performed using a patterned photoresist as a mask to expose the sub-collector layer 101. The configuration of FIG. 2C is thereby created.
Then, the collector electrode 109 is formed on the sub-collector 101 by the evaporation and lift-off process. The configuration of FIG. 2D is thereby created.
After that, the element insulating region 110 shown in FIG. 1A is created by ion implantation with boron and so on, using a photoresist as a mask. It allows insulation of the sub-collector layer 101 between elements. Alternatively, the recess-shaped element insulating region 111 shown in FIG. 1B may be formed by etching the sub-collector layer 101. It also allows insulation of the sub-collector layer 101 between elements.
As described above, reduction of the collector resistance is critical to increase the amplifier efficiency of the semiconductor device. The access resistance constituting part of the collector resistance is determined by sheet resistance of the sub-collector layer. The sheet resistance can be reduced by increasing the thickness of the sub-collector layer or by increasing the impurity concentration of the sub-collector layer. Currently, a normal thickness of the sub-collector layer is in the range of 100 to 700 nm, and a normal doping concentration is in the range of 1*1018/cm3 to 6*1018/cm3.
If the thickness of the sub-collector layer exceeds the above range, it is difficult to completely insulate the sub-collector layer between elements by ion implantation with boron and so on. Though the ion implantation with proton, helium and the like allows deep implantation, it degrades reliability.
In the case of insulating the sub-collector layer between elements by a recess, it is necessary to form a recess whose depth equals the thickness of the sub-collector layer. Thus, if the sub-collector layer is thick, a step height on the sub-collector layer is large. This poses a problem for the subsequent manufacturing process such as planarization.
If, on the other hand, the doping concentration of the sub-collector layer exceeds the above range, it causes problems such as decrease in current gain and degradation in reliability.
Japanese Unexamined Patent Application Publication No. 2002-299603 (Tanomura, et al.) describes a heterojunction semiconductor device which overcomes problems of instable collector resistance in high-temperature testing and so on while the collector resistance is reduced as low as possible and eliminates the dislocation into a base layer to increase current gain or enhance reliability while minimizing the collector resistance. Tanomura teaches to form the delta-doped sheet region of a given concentration between the collector layer and the collector electrode on the surface of the sub-collector layer.
However, Tanomura does not mention the insulation between device elements.
As described above, the present invention has recognized that conventional heterojunction semiconductor devices have a problem that increasing the thickness of the sub-collector layer for higher amplifier efficiency sacrifices the insulation of the sub-collector between device elements.